Turning to FIGS. 1 and 2, an example of a conventional POR circuit 100 and its desired performance can be seen. Typically, the POR circuit 100 is intended to provide a reset or reset signal during times of applied ramp up of the voltage on rail VDD. This can allow logic and other circuitry within a system in which the POR circuit 100 is employed to be reset to a default state during ramp up of the voltage on rail VDD or to restore the default state during a “brownout” event. To do this, the POR circuit 100 has two characteristic voltages: high threshold PORH and a low threshold PORL. The high threshold PORH is the “release threshold,” where the POR circuit 100 releases the reset signal as the voltage on rail VDD is increasing or ramping up to the nominal voltage VDDN, and the low threshold PORL is the “activate threshold,” where the reset signal is asserted as the voltage on rail VDD is decreasing or ramping down. The low threshold PORL is a lower voltage than high threshold PORH so as to provide a hysteresis to prevent “bouncing” of the reset signal POROUT if the voltage on rail VDD is near the threshold.
When the voltage on voltage rail VDD is rising or ramping up (i.e., between times T1 and T2 and between times T7 and T8), the POR signal POROUT (which is an active low reset signal) transitions from logic low (or “0”) to logic high (or “1”) once the voltage on rail VDD becomes greater than high threshold PORH (and which eventually reaches a nominal voltage VDDN). Typically, this ramping up or increase in the voltage occurs during power-up (i.e., between times T1 to T2) or following a “brownout” event (i.e., between times T12 and T13). In the structure shown in FIG. 1, this high threshold PORH is set by the characteristics of transistors Q1 and Q4 and resistor R1. Looking first to transistor Q1 (which, as shown is a PMOS transistor), the drain current ID, in saturation, for transistor Q1 is:
                                          I            D                    =                                                    1                2                            ⁢                              (                                                                            W                      L                                        ·                    μ                                    ⁢                                                                          ⁢                                      C                    OX                                                  )                            ⁢                                                (                                                            V                      GS                                        -                                          V                      TP                                                        )                                2                                      =                                          k                2                            ⁢                                                (                                                            V                      GS                                        -                                          V                      TP                                                        )                                2                                                    ,                            (        1        )            where VGS is the gate-source voltage of transistor Q1, VTP is the threshold voltage for transistor Q1, W/L is the aspect ratio (channel width to length) of transistor Q1, μ is the charge-carrier mobility, and COX is the gate oxide unit capacitance. So, as a result of configuration of POR circuit 100, the POR circuit 100 is released when:R1·ID≧VTN,  (2)where VTN is the threshold voltage of transistor Q4 (which, as shown, is an NMOS transistor). Substituting equation (1) into equation (2) and solving for the gate-source voltage VGS of transistor Q1 (which is the high threshold PORH), the high threshold PORH is:
                              V          GS                =                  PORH          =                                    V              TP                        +                                                                                2                    ⁢                                          V                      TN                                                                            R                    ⁢                                                                                  ⁢                                          1                      ·                      K                                                                                  .                                                          (        3        )            From equation (3), it can be seen that the high threshold PORH is a function of the relationship between resistor R1 and transistor Q1, namely the relative strength between resistor R1 and transistor Q1. By relative strength, this refers to how “strong” or “weak” the transistor Q1 and resistor R1 are with respect to one another. For example, if resistor R1 is large (i.e., up to 10's of MΩ), transistor Q1 would be a correspondingly “weak” transistor (i.e., having a low aspect ratio relative to resistor R1) to achieve the desired high threshold PORH. As an example, if the resistor R1 is on the order of 10's of MΩ, then the aspect ratio for transistor Q1 would be in the neighborhood of 1/10 for a 0.5 μm process node. A “strong” transistor for this example might have an aspect ratio of 10/1. Typically, R1 is on the order of 10's of MΩ to reduce power consumption, causing transistor Q1 to have a low aspect ratio (i.e., about 1/10) in order to achieve the desired high threshold PORH. Also, transistor Q4 of inverter 102 is usually set to be a “strong” transistor, while transistor Q3 of inverter 102 is set to be a “weak” transistor (i.e., having a low aspect ratio relative to transistor Q4). Because the resistance of resistor R1 can vary with process and temperature and because transistor Q1 is usually a “weak” transistor (which is highly susceptible to process and temperature variation independent of the variations in resistor R1), the relative strength (and, thus, the threshold PORH) can vary substantially due to process variations. This means that, for the POR circuit 100, the high threshold PORH is poorly controlled.
Once the voltage on rail VDD is greater than the high threshold PORH, transistor Q2 is able to turn “on,” providing a hysteresis. The POR circuit 100 can then reassert the POR signal POROUT as the voltage on rail VDD begins to fall or ramp down during, for example, power down or a “brownout” event (i.e., at times T4 and T10). The low threshold PORL is typically set by the characteristics of transistor Q2. Typically, transistor Q2 is a “strong” transistor (i.e., having a high aspect ratio relative to resistor R1). For example, transistor Q2 may have an aspect ratio of 10/1 for 0.5 μm process node when resistor R1 is on the order of 10's of MΩ. As a result, the low threshold PORL is approximately equal to the threshold voltage VTP of transistor Q2. Additionally, there can be a threshold voltage mismatch between transistors Q1 and Q2 that can create an extra variation in the hysteresis voltage (which is generally the difference between the high threshold PORH and the low threshold PORL). As a result, the “brownout” performance may suffer due to the poor control of the hysteresis voltage.
Thus, there is a need for an improved POR circuit.